Baya Systems is seeking an experienced Sr. Formal Verification specialist to join the DV team in England, United Kingdom. This position will be onsite at a strategic office location yet to be determined. Overall, we are looking for at least 6/7 years of industry experience. Responsibilities

Develop detailed formal verification (FV) test plans based on design specifications and collaborate with design teams to refine micro-architecture specifications. Identify key logic components and critical micro-architectural properties essential for ensuring design correctness. Implement formal verification models, abstractions, assertions, and utilize assertion-based model checking to detect corner-case bugs. Apply complexity reduction techniques using industry-standard EDA tools or academic formal verification tools to achieve proof convergence or sufficient depth. Develop and maintain scripts to enhance FV productivity and streamline verification processes. Assist design teams with the implementation of assertions and formal verification testbenches for RTL at unit/block levels. Participate in design reviews and collaborate with design teams to optimize design quality and performance, power, and area (PPA) metrics based on formal analysis feedback.

Qualifications

Strong proficiency in System Verilog/Verilog. Good scripting abilities with Python or Perl.

Preferred Experience

Hands-on experience with formal verification tools such as Synopsys VCFormal and Cadence JasperGold. Experience with both bug hunting and static proof verification techniques. Familiarity with automating formal verification workflows within a CI/CD environment.

For those interested, please apply to the job posting below or contact: Manager, Talent Acquisition Job details

Seniority level: Mid-Senior level Employment type: Full-time Job function: Engineering and Other Industries: Computer Hardware Manufacturing, Semiconductor Manufacturing, and Software Development

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