Join to apply for the Digital Design Engineer - Verification role at Flux Computing

Join to apply for the Digital Design Engineer - Verification role at Flux Computing

Flux Computing designs and manufactures optical processors to train and run inference on large AI models. Join us to be part of a highly motivated and skilled team that thrives on delivering impact and innovation at speed.

The Role

We’re searching for a Digital Design Engineer who is passionate about building and verifying complex, high‑performance ASICs. You will own the definition and execution of verification strategies for the digital subsystems that control, configure and monitor Flux’s optical datapaths and AI compute fabrics. Your work will ensure first‑silicon success and robust, production‑worthy silicon that scales to data‑centre volumes.

Responsibilities

• Architect, implement and maintain comprehensive verification environments (SystemVerilog + UVM, assertion‑based and formal) for datapath, control, memory and high‑speed I/O blocks in our OTPU.
• Define verification plans that target functional correctness, low‑power modes, safety, reliability and security requirements; derive and track coverage metrics to closure.
• Develop reusable VIP and stimulus generators for modules such as network‑on‑chip routers, DDR/LPDDR controllers, PCIe/CXL interfaces and proprietary photonic control logic.
• Collaborate closely with RTL designers to iterate on micro‑architectures, resolve corner‑case bugs and balance PPA (power, performance, area) trade‑offs uncovered during verification.
• Drive RTL quality → GDS sign‑off: run lint, CDC/RDC, SDC constraint validation, gate‑level simulations, GLS with SDF, and power‑aware checks; work with physical‑design teams on ECOs.
• Enable post‑silicon bring‑up by generating test vectors, configuring scan/DFT hooks, and supporting FPGA/emulation platforms for firmware and software teams.
• Mentor junior engineers on verification methodology, code reviews, and best practices; champion continuous‐integration flows, regressions and results dashboards.
• Track industry advances in formal verification, emulation, coverage‑driven flows, RISC‑V vectors, and AI‑centric design techniques to keep Flux at the forefront of silicon quality.
  
  

• 3+ years in digital ASIC/SoC design & verification, with at least two tape‑outs.
• Mastery of SystemVerilog/UVM, functional coverage, constraint‑random stimulus and scoreboards.
• Deep understanding of clock‑domain crossing, reset and power‑domain management, DFT/scan and low‑power (UPF/CPF) methodologies.
• Strong scripting (Python, Tcl, shell) to automate regressions and data analysis.
• Proven debug skills across RTL, gate‑level and emulation environments.
  
  

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Job function

  Engineering and Information Technology

• Industries

  Semiconductor Manufacturing

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