Rigpa.ai, Cambridge, United Kingdom Rigpa.ai is a fabless chip design start-up focusing on the next-generation AI ASIC chips. These chips are designed to accelerate future AI applications at 10x faster speed with a fraction of the power. Role Description This is a full-time on-site role for a Digital IC Design Engineer at all levels. The role is located in Cambridge or Edinburgh. The Digital IC Design Engineer will be responsible for designing, developing, and testing digital IC designs, creating digital circuit designs and RTL coding. The engineer will also be involved in validating and debugging digital designs, collaborating with the team to ensure the timely delivery of the projects. Qualifications

Experience in Digital Designs, Digital Circuit Design, and Circuit Design Skills in Digital IC Design and RTL Coding Ability to collaborate effectively within a team and work on-site Strong problem-solving skills and attention to detail Bachelor's or Master's degree in Electrical Engineering or related field Experience in AI chip design is a plus

Join our silicon design team working on cutting‑edge AI ASIC. You will help define and implement the digital microarchitecture of the next-gen AI chip. Key responsibilities

Design and implement microarchitectures for high‑performance AI ASIC cores, including processing engines, memory hierarchies and interconnects. Work closely with architects, verification, and software teams to specify features, create design documentation, and plan trade-offs between performance, power, and area. Contribute to system-level architecture exploration, model behaviour, and participate in power, performance, and timing analysis to optimise accelerator efficiency. Support chip integration and tape‑out by collaborating with backend teams on timing constraints and physical design considerations. Bachelor’s or Master’s in Electrical/Computer Engineering or related discipline. Experience with digital IC design for NPUs, GPUs or AI accelerators; multiple ASIC tape‑outs preferred. Proficiency in RTL coding (SystemVerilog/Verilog) and EDA tools for simulation and synthesis. Knowledge of high‑speed digital and low‑power design techniques, memory interfaces (HBM/DDR5) and standard protocols such as PCIe. Experience with micro‑architecture trade‑off analysis, performance modelling. Scripting skills in Python or TCL.

Join us in building the most advanced hardware for superintelligence. Looking for an opportunity but don't see a role? Reach out to hr@rigpa.ai #J-18808-Ljbffr