MyclientisagloballyrecognisedsemiconductorcompanydevelopinganewproductfamilybasedonRISC-Varchitecture,markingasignificantevolutionintheirtechnologyroadmap. TheyreseekingskilledverificationengineerstosupporttheincreaseddemandforfunctionalverificationacrossavarietyofcomplexIPs.Thisgrowthreflectsbothlong-terminvestmentinR&Dandastrategicshiftinarchitecture,makingitanexcitingtimetojoin. PrincipalVerificationEngineer Responsibilities: DevelopandmaintainSystemVerilogUVMtestbenchesforcomplexIPs. LeadthecreationofnewUVMverificationcomponentsandcontributetotestbencharchitecture Debugtestfailuresanddefinefunctionalcoveragemodelstoensuresign-offquality. Workcloselywithdesignersandcontributetoverificationstrategyduringdesignandconceptphases. Improveverificationefficiencyandensurecompliancewithfunctionalsafetyandqualitystandards. Requirements: Minimum5yearsofIP-levelverificationexperienceusingSystemVerilogUVM. StrongunderstandingofUVMmethodology,SVAs,andverificationmetrics. Abilitytointerpretcomplexdesignspecificationsandcreaterobustverificationenvironments. Proficiencyinindustry-standardEDAtoolsandscriptinglanguages. Excellentcommunicationskillsandamethodical,detail-focusedapproach. Applytolearnmore!

AMRT1_UKTJ ...