Overview

Senior Digital IC Design Engineer role at Power Integrations.

Reports to: Senior Digital Design Manager

Objective Of The Role

Based in our Cambridge office you will work closely with colleagues in both the IC Design and Product Definition teams to provide solutions required for the digital elements of the mixed signal products developed by Power Integrations. This will include solutions which satisfy test and manufacturing requirements. In addition, you will work in developing behavioural models to help accelerate simulation or form part of system emulation.

Education And Work Experience

• MSc/MEng or PhD in Electronics Engineering or related subject.
• Minimum 3 years experience in digital IC design using standard cell libraries.

As a Digital Designer You Should

• Have in depth knowledge and understanding of best-practice digital design methods.
• Be familiar executing designs via a fully synthesised digital design flow with RTL and logic synthesis.
• Be fully conversant with the SystemVerilog standard and scripting languages such as TCL.
• Be familiar with the use of constraints and the automatic place-and-route flow for the physical design.
• Understand the importance of production test and have experience of design methods to maximize test coverage such as scan.
• Have experience of design techniques for optimising digital power consumption.
• Have experience of debugging digital functions in a lab using suitable test equipment (e.g. mixed-signal oscilloscopes).
• Have experience producing accurate and complete documentation.

Main Responsibilities

• Development of functional digital blocks and contribution to complete mixed signal ASICs from definition to full production maturity.
• Support the Product Definition team with feasibility study, product architecture definition and digital blocks design for FPGA emulation.
• Complete RTL design in SystemVerilog of digital functions to meet all specification requirements.
• Create suitable block-level test benches for comprehensive verification of all digital blocks.
• Create suitable behavioural models and top-level test benches for comprehensive verification and regression of all system-level functions and production test functions.
• Complete digital synthesis with suitable physical constraints to meet all PPA requirements.
• Define and implement DFT architecture. Perform scan insertion, ATPG and insert test points to achieve the required test coverage.
• Define digital layout floorplan, oversee digital place-and-route, and ensure post-layout timing closure.
• Generate all necessary design documentation and participate in design reviews.
• Contribute to all product-level verification and validation plans.
• Support silicon evaluation and all product validation activities working with Product, Quality and Test Engineering up to production ramp-up.
• Contribute to Technology Process and Design Methodology improvements.

What We Offer You

• Health & Wellbeing: Private healthcare (option to add on immediate family members)
• Enhanced Sick Pay
• Group Income Protection scheme
• Employee Assistance Programme through ‘We Care’
• Group Life scheme (x4 salary)
• Cycle2Work – savings of at least 32% on a new bike or accessories
• Employee perks: discount on trips, hotels, gyms, days out, restaurants, supermarkets and more.

Financial Incentives

• ESPP (employee stock purchase plan) – Option to join scheme twice a year
• Pension scheme - A contributory private pension
• Generous Employee referral bonus

25 days paid holiday (exclusive of Bank Holidays) and free onsite parking

Seniority level

• Mid-Senior level

Employment type

• Full-time

Job function

• Engineering and Information Technology
• Industries: Semiconductor Manufacturing

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