Job Description

Senior Physical Design Engineer - Semiconductors / Inside IR35

We are currently partnered with an industry leading semiconductor company in the UK looking to expand their team with an experienced Physical Design Engineer to join their GPU team in Cambridge.

This opportunity in a hybrid contract engagement (2 days onsite in Cambridge required) with an initial duration of 6 months (Inside IR35).

Key Responsibilities:

• Perform full physical implementation flow of complex processor designs, from RTL through place and route to static timing analysis (STA).
• Provide constructive feedback to RTL designers to enhance PPA and remove implementation bottlenecks via issue tracking tools.
• Collaborate with EDA tool vendors to troubleshoot tool-related challenges and improve design outcomes.
• Manage and prioritize your workload to meet project milestones and objectives.

Required Experience & Tools:

• Experience with Cadence tools such as Genus, Innovus, Tempus, QRC, and Conformal.
• Proficient in physical design flows including synthesis, logical equivalence checking (LEC), floorplanning, placement, clock tree synthesis (CTS), routing, and STA.
• Familiarity with Synopsys Fusion Compiler and Formality tools.
• Knowledge of low power design methodologies including power gating and dynamic voltage and frequency scaling (DVFS).
• Ability to develop and maintain automation scripts using TCL, Python, or Perl to support project workflows.

Keywords: Physical Design, RTL, Place and Route (PnR), Static Timing Analysis (STA), Logical Equivalence Checking (LEC), Low Power Design, Power Gating, DVFS, Cadence Genus, Cadence Innovus, Cadence Tempus, QRC, Conformal, Synopsys Fusion Compiler, Formality, Synthesis, Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, UPF, Constraint Development, EDA Tools, Automation Scripting, TCL, Python, Perl, Semiconductor, GPU Design

If you are interested in this Senior Physical Design Engineer position, please send a copy of your CV to ts@eu-recruit.com

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